This invention is in the field of solid-state memory of the ferroelectric type. Embodiments of this invention are directed to circuit techniques for improving read margin, and reducing power consumption and memory cycle times, in ferroelectric random access memories (FRAMs).
Many modern electronic devices and systems now include substantial computational capability for controlling and managing a wide range of functions and useful applications. Many of these electronic devices and systems are now portable or handheld devices. For example, many mobile devices with significant computational capability are now available in the market, including modern mobile telephone handsets such as those commonly referred to as “smartphones”, personal digital assistants (PDAs), mobile Internet devices, tablet-based personal computers, handheld scanners and data collectors, personal navigation devices, implantable medical devices, and the like.
A recently developed technology for realizing non-volatile solid-state memory devices involves the construction of capacitors in which the dielectric material is a polarizable ferroelectric material, such as lead zirconate titanate (PZT) or strontium-bismuth-tantalate (SBT). Hysteresis in the charge-vs.-voltage (Q-V) characteristic, based on the polarization state of the ferroelectric material, enables the non-volatile storage of binary states in those capacitors. In contrast, conventional MOS capacitors lose their stored charge on power-down of the device. It has been observed that ferroelectric capacitors can be constructed by processes that are largely compatible with modern CMOS integrated circuits, for example by forming the capacitors above the transistor level, between overlying levels of metal conductors.
Ferroelectric technology is now utilized in on-volatile solid-state read/write memory devices. These memory devices, commonly referred to as “ferroelectric RAM”, or “FeRAM”, or “FRAM” devices, now appear in many electronic systems, particularly portable electronic devices and systems. FRAM memories are especially attractive in implantable medical devices, such as pacemakers and defibrillators.
As known in the art, FRAM cells may be implemented in various forms, including as a one-transistor, one-capacitor (1-T, 1-C) memory cell similar to a typical DRAM cell. Other implementations include 2-T, 2-C cells, in which the two capacitors differentially define the stored data state, and six-transistor (6-T) SRAM cells that include one or two ferroelectric capacitors that are programmed to retain the SRAM data state after power is removed.
FIG. 1a illustrates the construction of a conventional 1-T, 1-C FRAM memory cell 4, as is now typically used in modern FRAMs. Ferroelectric capacitor 5 serves as the non-volatile memory element, and is constructed as a parallel-plate solid-state capacitor with ferroelectric dielectric material, such as PZT, as the capacitor dielectric. In this example, FRAM cell 4 resides in row j and column k of an array of similarly constructed FRAM cells 4. One plate of capacitor 5 is connected to plate line PLj for the jth row of the array, and the other plate of capacitor 5 is connected to one end of the source/drain path of n-channel metal-oxide-semiconductor (MOS) transistor 6. The other end of the source/drain path of transistor 6 is connected to bit line BLk for the kth column of the array, and the gate of transistor 6 is connected to word line WLj of the jth row of the array. As such, transistor 6 serves as a pass transistor in the DRAM sense, connecting ferroelectric capacitor 5 to bit line BLk upon selection of row j according to a row address that indicates energizing of word line WLj.
As mentioned above, the data storage mechanism of FRAM cells is the charge-voltage hysteresis of the ferroelectric capacitor dielectric. FIG. 1b illustrates an example of a Q-V characteristic of a conventional ferroelectric capacitor, such as capacitor 5 in cell 4 of FIG. 1a. As shown, the charge (Q) stored across the conductive plates depends on the voltage applied to the plates (V), and also on the recent history of that voltage. If the voltage V applied across the capacitor plates exceeds a “coercive” voltage +Vα, the capacitor polarizes into the “+1” state. According to this characteristic, once polarized to the “+1” state, so long as voltage V remains above coercive voltage −Vβ, the capacitor exhibits a stored charge of +Q1. Conversely, if an applied voltage V is more negative than coercive voltage −Vβ, the capacitor is polarized into the “−1” state, and will exhibit a stored charge of −Q2.
An important characteristic of ferroelectric capacitors, for purposes of non-volatile storage in integrated circuits, is the difference in capacitance exhibited by a ferroelectric capacitor its two polarized states. As fundamental in the art, the capacitance of an element refers to the ratio of stored charge to applied voltage. In the context of a ferroelectric capacitor, the change in polarization state that occurs upon application of a polarizing voltage is reflected by the amount of charge stored by the capacitor as a result. As shown in FIG. 1b, the polarization of ferroelectric capacitor 5 from its “−1” state to its “+1” state is reflected by a relatively high capacitance C(−1), reflecting significant polarization charge that is stored as a result of the change of polarization state as the voltage exceeds its coercive voltage Vα. On the other hand, if capacitor 5 is already in its “+1” state, little polarization charge is stored as a result of the application of that voltage, and thus the capacitance C(+1) is relatively small, since the ferroelectric domains of capacitor 5 are already aligned prior to the application of the voltage. As such, the stored data state in FRAM cell 4 can be read by interrogating the capacitance of ferroelectric capacitors to discern its previous polarized state.
FIG. 2 is a timing diagram illustrating the reading and writing of FRAM cell 4 of FIG. 1a, in a conventional FRAM. As well-known in the art, sensing of the state of 1-T, 1-C memory cells (such as in DRAMs and FRAMs) is carried out by a differential MOS sense amplifier connected on one side to a bit line BLk and on another side to a reference voltage that is set approximately half-way between the “0” and “1” data states (e.g., as established by a “dummy” cell). The cycle shown in FIG. 2 begins with the precharge of bit line BLk to a ground voltage (near 0 volts in this example), with both word line WLj and plate line PLj also near ground. Word line WLj is then energized to a high voltage (e.g., at or near power supply voltage Vdd), upon a received memory address indicating row j for access. In this conventional operation, a three-pulse operation is performed within each pulse of word line WLj. The first pulse in this sequence is a “read” of cell 4 in row j and each column k (one of which is shown in FIG. 2), initiated by plate line PLj being driven to a high voltage.
In this “read” pulse, referring back to FIGS. 1a and 1b, plate line PLj is driven to a high voltage during the word line pulse, with bit line BLk having been precharged to ground. Considering the voltage V of the Q-V curve of FIG. 1b as corresponding to the voltage differential between plate line PLj and bit line BLk (i.e., VPL−VBL), this pulse of plate line PLj amounts to raising of the voltage V above 0 volts, toward “coercive” voltage +Vα. If capacitor 5 is in its “−1” polarization state, this plate line pulse will cause capacitor 5 to exhibit capacitance C(−1), transferring charge to bit line BLk; conversely, if capacitor 5 is in its “+1” state, the plate line pulse will follow capacitance C(+1), transferring much less charge to bit line BLk. This charge transfer develops a voltage response at bit line BLk as shown in FIG. 2 by plots BLk(D1) for the “1” data state (resulting from the “−1” polarization state) and BLk(D0) for the “0” data state (resulting from the “+1” polarization state).
In most modern FRAMs of this construction, plate line PLj is then de-energized after the charge transfer to bit line BLk, after which the differential sense amplifier senses the transferred charge (by determining the polarity of the differential voltage between bit line BLk and a reference level), and develops its full differential data state as a result. This “off-pulse” sensing has been observed to provide better read margin than “on-pulse” sensing (i.e., flipping of the sense amplifier during the plate line pulse), because the bit line voltages are charged above ground for both data states during the “read” pulse, as shown in FIG. 2.
In either data state, the read of FRAM cell 4 in this manner is destructive, in that capacitor 5 is at least partially polarized by this operation. Conventional FRAM operation thus restores the sensed data state. In the conventional approach of FIG. 2, the “0” data state is written to every FRAM cell 4 in row j, by again pulsing plate line PLk to a high voltage while holding bit line BLk (and all bit lines corresponding to cells 4 in the selected row j) at ground. This pulse writes a “0” to each of these cells 4, by applying a full voltage beyond coercive voltage +Vα across each ferroelectric capacitor 5. Following this unconditional “0” write pulse, a “1” data state is then written into those FRAM cells 4 in this row j that previously stored a “1” data state. This write “1” pulse consists of holding plate line PLj low for row j, while driving bit lines BLk corresponding to those “1” data state cells 4 to a high voltage. This operation applies a negative voltage beyond coercive voltage −Vβ (FIG. 1b) across the corresponding capacitors 5, polarization those capacitors into the “−1” state. Of course, the selection of which bit lines BLk receive this “1” write pulse can be modified from that indicated by the sensed data states, for example in a read-modify-write operation or as a result of error correction.
This conventional FRAM memory operation has been observed to provide reasonably good data stability and performance. However, as evident from FIG. 2, the necessity to perform the multiple pulses and intervals within each read cycle (“read”, “sense”, “write 0”, “write 1”) limits memory performance by requiring relatively long cycle times.
By way of further background, commonly assigned U.S. Pat. No. 7,733,682 B2, incorporated herein by this reference, describes a ferroelectric memory having a plate line driver circuit that applies a “boost” voltage, above the power supply voltage, to the plate lines of the memory during memory access. As described therein, application of the “boost” plate line voltage during the “read” operation results in better read margin.